1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more particularly, it relates to a semiconductor circuit device having a hierarchical power supply structure according to an SCRC (subthreshold leakage current reduced control) technique.
2. Description of the Prior Art
A semiconductor circuit device having a hierarchical power supply structure is provided with a main power supply line and a sub power supply line, with a P-channel MOS transistor connected therebetween. The semiconductor circuit device is further provided with a main ground line and a sub ground line, with an N-channel MOS transistor connected therebetween. A logic circuit such as an invertor outputting a logical high-level signal in a standby state is connected between the main power supply line and the sub ground line, while a logic circuit such as an invertor outputting a logical low-level signal in the standby state is connected between the sub power supply line and the main ground line.
In an active state, both the P- and N-channel MOS transistors are turned on and hence the voltage of the sub power supply line reaches a power supply voltage identically to the main power supply line, while the voltage of the sub ground line reaches a ground voltage identically to the main ground line. Therefore, the aforementioned logic circuit outputs a high- or low-level signal in response to an input signal as general.
In the standby state, on the other hand, both the P- and N-channel MOS transistors are turned off and hence no power supply voltage is supplied to the sub power supply line and no ground voltage is supplied to the sub ground line. While the logic circuit connected to the main power supply line can normally output a high-level signal, a subthreshold current flowing in this logic circuit is reduced since the sub ground line is disconnected from the main ground line. While the logic circuit connected to the main ground line can normally output a low-level signal, a subthreshold leakage current flowing in this logic circuit is also reduced since the sub power supply line is disconnected from the main power supply line.
In the standby state, however, the sub power supply line and the sub ground line are disconnected from the main power supply line and the main ground line respectively and hence the voltage of the sub power supply line lowers to increase the potential difference between the main power supply line and the sub power supply line. Further, the voltage of the sub ground line increases to also increase the potential difference between the main ground line and the sub ground line. When the semiconductor circuit device shifts from the standby state to the active state and the sub power supply line is shorted to the main power supply line, therefore, it takes time for the voltage of the sub power supply line to reach the power supply voltage. Further, it also takes time for the voltage of the sub ground line to reach the ground voltage when the sub ground line is shorted to the main ground line. Consequently, the operating speed of the logic circuit is disadvantageously slowed down.
In order to solve this problem, U.S. Pat. No. 5,659,517 discloses a voltage set circuit for setting a sub power supply line at a reference voltage Vref1 while setting a sub ground line at a reference voltage Vref2. While this voltage set circuit can prevent a voltage drop of the sub power supply line and a voltage rise of the sub ground line in a standby state, a subthreshold leakage current flowing in a logic circuit disadvantageously increases. In other words, no sufficient effect of reducing the subthreshold leakage current can be attained by disconnecting the sub power supply line and the sub ground line from a main power supply line and a main ground line respectively.
U.S. Pat. No. 5,724,297 discloses a transistor for temporarily shorting a sub power supply line and a sub ground line when an internal circuit shifts from an active state to a standby state, in order to reduce current consumption. However, this gazette discloses no means for charging the sub power supply line and the sub ground line.